基于FPGA的FIR数字滤波器设计_电子信息工程.rar

摘要

　　　在近代，滤波器逐渐成为电信设备和各类控制系统中，一个不可缺少的组成部分，应用已经极为广泛，适用于通信处理、语音处理、图像处理、自动控制，在军事、医疗设备和家用电器上等各方各面。早期的滤波器只能满足设计简单、结构简便的要求，通过不断地研究，衍生出一个新的分支，就是数字滤波器。

　　　自从FPGA在约二十世纪出现以来，为数字滤波器的设计和实现创造出一条崭新的道路。不过，单独设计一个满足技术指标的数字滤波器是一件有挑战性的设计任务，需要一些软件的辅助，例如，MATLAB、QUARTUSII等软件。

　　　在论文中，设计是基于FPGA的FIR数字滤波器，设计过程中实现低通滤波，采样频率为45kHz，截止频率为10.5kHz，通带截止频率处的幅值衰减小于6db，输入输出为8位二进制数。

　　　论文首先介绍了本文的研究背景，然后介绍现场可编程门阵列（FPGA）和硬件描述语言（VHDL），之后介绍了数字滤波器的设计原理，并提出本文采用的设计方法，最后对设计进行仿真。仿真结果表明：本17阶FIR数字滤波器设计能够实现截止频率为10.5kHZ的低通滤波。

关键词：数字信号处理；数字滤波器；现场可编程门阵列；硬件描述语言

Abstract

　　　Nowadays, the filter is the indispensable part of the tele-communication equipment and types of control system and it has been widely used. It adapts to use in the communication processing, voice processing, image processing, auto-control. In early period, the filter’s circuit was simple, so it just could design something easily. Though the designers research again and again on the filters’ design, a new branch is created which is the digital filter.

　　　Since the FPGA appeared nearly in the twentieth century, it has created a new way for the design and implementation of the digital filter. However, designing a digital filter to meet the technical indicators is a challenging task by myself. I need some software to assist me, for example, MATLAB, QUARTUS II and others.

　　　In the papers, the design is the FIR digital filter based on FPGA to implement the low-pass filter which sampling frequency is 45kHz, cut-off frequency is 10.5kHz, pass-band amplitude attenuation at the cut-off frequency is less than 6db, input and output is 8 bit in two-tier system.

　　　Paper first introduces the research background, then it describes field programmable gate array (FPGA) and hardware description language (VHDL). Next comes the principle and design of digital filter and it proposes the design method, finally the design can be simulated. The result of the design’s simulation shows that, the 17-order FIR digital filter can implement the low-pass filter which cut-off frequency is 10.5kHz.

Keyword: Digital signal processing; Digital filter; FPGA; Hardware description language.